During STI formation, CMP of an overlying STI oxide layer in the formation of STI structures generally leads to dishing or preferential polishing of the upper portion of the STI structure in relation to surrounding surfaces.
In addition, in logic and mixed signal operations, device elements such as resistors are formed in an active device area. Prior art methods have proposed forming dummy areas surrounding active areas to avoid dishing effects in CMP processes to form STI structures as well as improve the uniformity in polysilicon e.g., gate electrode etching processes.
However, a problem in the prior art is that the formation of dummy patterns has been found to undesirably affect the electrical performance of devices formed in the active areas by parasitic coupling phenomena.
There is therefore a need in the semiconductor device integrated circuit manufacturing art to develop an improved method to form dummy patterns to avoid active device performance degradation.
It is therefore an object of the invention to provide an improved method to form dummy patterns to avoid active device performance degradation, while overcoming other deficiencies and shortcomings of the prior art.